Non-volatile data storage devices, such as flash solid state drive (SSD) memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 2 bits per cell, 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g., “parity bits”) that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases. Using a sufficient number of parity bits to provide “worst-case” error correction capability for all data stored in a memory device reduces the storage density of the memory device in order to protect against an amount of data corruption that is statistically unlikely to occur before the memory device reaches the end of its useful life.
SSD devices may also incorporate a redundant array of independent dies (RAID)-type storage scheme that may use parity bits to enable data recovery in case of memory defects and device failures, which cannot be recovered by the ECC which is aimed at handling random errors (e.g., due to program disturb, read disturb, charge loss due to data retention, etc.). ECC may not be able to recover the data in case of memory defects or complete failure, which may result in very high error rates that exceed the ECC capability. Hence, additional RAID-type protection may be required for protecting against such memory defects. For example, a RAID 6 storage scheme may distribute data, a first parity for the data, and a second parity for the data in a “stripe” across multiple non-volatile memories (e.g., across multiple SSDs or across multiple NAND flash memories in a single SSD). The first parity (or the second parity) may enable recovery of the data in the stripe in case of erasures due to failure of one of the data-storing non-volatile memories, and the first parity and the second parity together may enable recovery of the data in the stripe in case of erasures due to failure of two of the data-storing non-volatile memories. However, data in such storage schemes may not be recoverable if three or more of the data-storing non-volatile memories fail. Note that although the name RAID may suggest that RAID parity is stored in a redundant die, this is not mandatory. In some cases, a redundant plane, redundant block or redundant word lines (WLs) or pages within a block may be used for storing the RAID parity. For example, the RAID stripe may be implemented across dies, planes, blocks or pages within a block of the non-volatile memory.
The two protection levels, ECC for random errors and RAID for memory defects and failures, may require memory overprovisioning for storing the ECC and RAID parity.
Additionally, as memory technologies change, there is a drive to improve latency between a memory and a controller (or between a data storage device and an access device). One way to improve latency is to reduce the amount of data transferred between the controller and the memory, such as by using an ECC scheme with fewer parity bits. However, reducing the number of parity bits may reduce the error correcting capacity of the ECC scheme.